Difference between Verilog Continuous and Procedural Assignment

Difference between verilog continuous and procedural assignment

The best way to understand the verilog continuous and procedural assignment is by looking at the examples.

Continuous Assignment Statement Examples

assign output1 = x1 & x2 ;

wire output1 = p1 & p2 ;

Procedural Assignment Statement Examples

always @ (posedge clk)

xyz <= in1 & in2 ;

always @ ( posedge clk or negedge reset)

if ( !reset) xyz <= 0 ;
else xyz = in1;

Here are the key points to know about the difference in the Continuous and procedural assignment statements

1. The continuous assignment statement is used to infer combinatorial logic. The procedural assignment statement is used to infer the combinatorial as well as the sequential logic including flip flops and latches.

2. The continuous assignment statement assigns value primarily to nets while the
procedural assignment statement assigns values primarily to reg element.

3. The variables are driven to the output continuously to the output in the continuous assignment statement. In the procedural assignment statement, the results of the calculation are stores in a variable.

Please follow and like us:

Add a Comment

Your email address will not be published. Required fields are marked *

error: Content is protected !!